1. Field of the Invention
Example embodiments of the present invention relate to semiconductor memory devices, for example, non-volatile memory (NVM) devices having resistance nodes.
2. Description of the Related Art
Non-volatile memory (NVM) devices may be classified as threshold voltage transition devices, charge displacement devices or resistance varying devices. Depending on the type of a storage node, threshold voltage transition devices may be classified as flash memory devices with a floating gate or SONOS devices with a charge trapping layer. Charge displacement devices may be classified as nano-crystal ferroelectric RAM (FRAM) devices or polymer devices. Resistance varying devices my be classified as magnetic RAM (MRAM) devices, phase change RAM (PRAM) devices, resistance RAM (RRAM) using a compound metal oxide or polymer memory devices.
For example, related art resistance nodes used in a resistance memory may comprise a SrZrO3 layer of which 0.2% may be doped with chromium (Cr).
FIGS. 1A and 1B are photographic images of an electron-beam-induced current (EBIC) of a related art resistance memory device and graphs illustrating current characteristics versus voltage characteristics relating to the EBIC. As shown, the resistance of a resistance node may vary as a sweeping voltage is applied to both terminals of the resistance node. The resistance node may vary from a higher resistance state (e.g., R=606 kΩ) in an initial stage as illustrated in FIG. 1A to a lower resistance state (e.g., R=10.5 kΩ) when a voltage is lowered less than −8 V as illustrated in FIG. 1B. White points in the EBIC photos indicate conductive paths.
Referring to the EBIC photos, since the resistance node varies from the higher resistance state to the lower resistance state, the white points which are the conductive paths may become larger (e.g., the white points indicated by arrows). The conductive paths may be locally (not wholly) formed on the resistance node when an amount of current flowing through the resistance node varies (e.g., when the resistance of the resistance node varies), as shown in FIGS. 1A and 1B.
FIG. 2 is a sectional view illustrating the shape of a filament of the resistance memory device of FIG. 1. Referring to FIG. 2, a conductive path 80 may be disposed between two electrodes 50 and 60 via a resistance node 70. The conductive path 80 may be formed in the shape of a filament as shown in FIGS. 1A and 1B.
FIG. 3 is a sectional view illustrating the shape of the filament of a related art NAND-type resistance memory device in a block erasure operation. As shown, when the resistance node 70 having a NAND structure is serially connected, the conductive path 80 in the shape of the filament may not be connected to the length direction of the resistance node 70. In this example, a resistance node region H may utilize the disconnected conductive path 80 has a higher resistance path, such that the resistance node 70 may not be easily changed to the lower resistance state. According to the related art, a NAND-type or AND-type resistance memory device having serially connected resistance node 70 may not be operated in a unit block at a time.